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課程名稱 |
交換電路與邏輯設計
Switching Circuit and Logic Design |
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開課學期 |
104-1 |
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授課對象 |
電機工程學系 |
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授課教師 |
江介宏 |
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課號 |
EE2012 |
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課程識別碼 |
901 32300 |
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班次 |
04 |
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學分 |
3 |
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全/半年 |
半年 |
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必/選修 |
必修 |
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上課時間 |
星期四7(14:20~15:10)星期五8,9(15:30~17:20) |
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上課地點 |
電二144電二144 |
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備註 |
本系優先
總人數上限：70人 |
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Ceiba 課程網頁 |
http://ceiba.ntu.edu.tw/1041EE2012_LD04 |
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課程簡介影片 |
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核心能力關聯 |
核心能力與課程規劃關聯圖 |
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課程大綱
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為確保您我的權利,請尊重智慧財產權及不得非法影印
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課程概述 |
「交換電路與邏輯設計」課程將介紹如何以「開關」(switch)作為實現布林邏輯與設計數位電路之基本元件，並介紹如何有系統地優化交換電路(switching circuit)。
課程內容包括：
Introduction
- Number Systems and Conversion
Boolean Algebra and its Applications
- Combinational Logic Design and its Minimization
- Karnaugh Maps and Two-Level Logic Minimization
- Multi-Level Gate Circuits
- Combinational Circuit Design
- Multiplexers, Decoders, and Programmable Logic Decices
Sequential Logic Design and its Minimization
- Latches and Flip-Flops
- Registers and Counters
- Analysis of Clock Sequential Circuits
- Derivation of State Graphs and Tables
- Reduction of State Tables
- Sequential Circuit Design
- Circuits for Arithmetic Operations
Hardware Description Language: Verilog (basics) |
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課程目標 |
數位系統在我們的日常生活中無所不再，「交換電路與邏輯設計」課程將帶領同學們進入「零」與「壹」的世界，了解二元邏輯如何能勝任所有的計算工作。
本課程將提供其他進階課程﹝如「數位積體電路設計」、「電子設計自動化導論」、「計算機組織與架構」、「邏輯合成與驗證」、「積體電路測試」等課程﹞之入門知識。 |
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課程要求 |
無預修科目
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預期每週課後學習時數 |
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Office Hours |
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指定閱讀 |
C. H. Roth Jr. Fundamentals of Logic Design, 7th Edition, Cengage Learning, 2013 |
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參考書目 |
待補 |
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評量方式
(僅供參考) |
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No. |
項目 |
百分比 |
說明 |
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1. |
Homework |
14% |
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2. |
Quiz 1 |
4% |
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3. |
Midterm Exam |
35% |
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4. |
Quiz 2 |
4% |
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5. |
Project |
6% |
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6. |
Final Exam |
35% |
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7. |
Participation |
2% |
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週次 |
日期 |
單元主題 |
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第1週 |
9/17,9/18 |
(9/17) §1 Introduction, Number Systems and Conversion
(9/18) §1 Introduction, Number Systems and Conversion; §2 Boolean Algebra |
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第2週 |
9/24,9/25 |
(9/24) §2 Boolean Algebra
(9/25) §3 Boolean Algebra (Continued) |
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第3週 |
10/01,10/02 |
(10/01) §4 Applications of Boolean Algebra
(10/02) §4 Applications of Boolean Algebra
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第4週 |
10/08,10/09 |
(10/08) §5 Karnaugh Maps
(10/09) (No lecture -- Pre-National Day) |
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第5週 |
10/15,10/16 |
(10/15) §5 Karnaugh Maps
(10/16) §7 Multi-Level Gate Circuits |
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第6週 |
10/22,10/23 |
(10/22) Quiz (§1 ~ §4)
(10/23) §8 Combinational Circuit Design (skip §8.1 and §8.2) |
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第7週 |
10/29,10/30 |
(10/29) [start at 13:20 to make up 11/05 lecture] §8 Combinational Circuit Design (skip §8.1 and §8.2)
(10/30) §9 Multiplexers, Decoders, and Programmable Logic Devices (skip §9.7) |
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第8週 |
11/05,11/06 |
(11/05) (lecture moved to 10/29) [§9 Multiplexers, Decoders, and Programmable Logic Devices (skip §9.7)]
(11/06) Combinational Circuit Design Using Altera Quartus II (held by TA) |
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第9週 |
11/12,11/13 |
(11/12) Review Session
(11/13) Midterm Exam (§1~§9) |
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第10週 |
11/19,11/20 |
(11/19) §11 Latches and Flip-Flops
(11/20) §11 Latches and Flip-Flops |
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第11週 |
11/26,11/27 |
(11/26) §12 Registers and Counters
(11/27) §12 Registers and Counters |
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第12週 |
12/03,12/04 |
(12/03) §13 Analysis of Clocked Sequential Circuits
(12/04) §13 Analysis of Clocked Sequential Circuits |
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第13週 |
12/10,12/11 |
(12/10) §14 Derivation of State Graphs and Tables (skip Examples 2, 3 of §14.3)
(12/11) §15 Reduction of State Tables (§15.1 ~ §15.3) |
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第14週 |
12/17,12/18 |
(12/17) Quiz 2 (§11 ~ §13)
(12/18) Sequential Circuit Design Using Altera Quartus II (held by TA) |
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第15週 |
12/24,12/25 |
(12/24) §16 Sequential Circuit Design (§16.1 ~ §16.4)
(12/25) §16 Sequential Circuit Design (§16.1 ~ §16.4) |
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第16週 |
12/31,1/01 |
(12/31) §16 Sequential Circuit Design (§16.1 ~ §16.4)
(01/01) (no lecture -- Happy New Year!) |
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第17週 |
1/07,1/08 |
(01/07) Presentation of Selected Projects [start at 13:20]
(01/08) Supplementary Materials |
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第18週 |
1/14,1/15 |
(01/14) Review Session
(01/15) Final Exam |
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